1. Field of the Invention
This invention relates to a multi-chip semiconductor device having a plurality of semiconductor chips formed thereon, and more particularly, to a multi-chip semiconductor device having a plurality of semiconductor chips of planar shapes of different sizes mounted thereon.
2. Description of the Related Art
A multi-chip semiconductor device is known which is obtained by stacking a logic chip such as ASIC on a semiconductor memory chip with large capacity in a face-to-face fashion and connecting the chips to each other by use of connection means such as bumps. In the above multi-chip semiconductor device, generally, the logic chip is used as a parent chip and the semiconductor memory chip is used as a child chip. The parent chip transfers signals with respect to the exterior of the chip. Therefore, it is necessary to lead out terminals for connection with the exterior from the parent chip. However, in a case where the planar shape of the parent chip is smaller than that of the child chip and the terminals for connection with the exterior of the parent chip are hidden by the child chip, the external terminals cannot be lead out from the parent chip.
In order to solve the above problem, for example, it is considered that a mounting substrate on which wirings are made to permit a plurality of semiconductor chips to be mounted thereon is prepared and a plurality of semiconductor chips are mounted on the mounting substrate in a planar form. However, with this method, the semiconductor device is made larger.
A semiconductor device having a plurality of semiconductor chips stacked in a thickness direction of the semiconductor chips with a film type substrate disposed therebetween is disclosed in Oka et al. (U.S. Pat. No. 6,861,760).